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3.4.2 Additional Logic Gates

        Multiple input gates: Consider the boolean function F = (x ● y) ● z. Fig 3.5 shows an implementation of the
        Boolean function F = (x ● y) ● z. using two AND gates.

                                         x
                                         y



                                                                    F = (x ● y) ● z



                                         z

                                   Fig 3.5: Logic Diagram for Boolean function F = (x ● y) ● z
        We often use multiple input AND and OR gates to simplify the logic diagrams. For example, Fig 3.5 may be simplified
        using a three input AND gate shown in Fig 3.6

                                              x
                                              y                  F = x ● y ● z
                                              z


                               Fig 3.6: Simplified Logic Diagram for Boolean function F = x ● y ● z
        NAND gate: NAND gate has the effect of applying an AND gate, followed by a NOT gate. Thus, A NAND B is equivalent to
        (A●B)'. The truth table and logic diagram for NAND gate are given in Table 3.8 and Fig 3.7, respectively.


                                    A                 B                  (A ● B)'
                                    0                 0                       1

                                    0                 1                       1
                                    1                 0                       1
                                    1                 1                       0
                                              Table 3.8 Truth table for NAND gate


                                      A
                                                                          A NAND B
                                      B
                                              Fig 3.7: Logic Diagram for NAND gate

        By De Morgan's law of Boolean algebra; we know that (A ● B)'= A' + B'. So, a NAND gate may also be implemented
        by negating the inputs, followed by the application of an OR gate as shown in Fig 3.9.






                      Fig 3.8: Logic Diagram for NAND gate           Fig 3.9: Logic Diagram for NAND gate

        NOR gate: NOR gate has the effect of applying an OR gate, followed by a NOT gate. Thus, A NOR B is equivalent to
        (A + B)'. The truth table and logic diagram for NOR gate are shown in Table 3.9 and Fig 3.10, respectively.






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