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2.6.2 8 × 1 Multiplexer
An 8 × 1 Multiplexer circuit has eight input lines, three selection lines and one output line. If the inputs are denoted
by A to A and the selection lines as S , S and S then the block diagram and truth table of a 8 × 1 Multiplexer will be
0
1
7
0
2
Input lines Output line
A 7
A 6 S 2 S 1 S 0 Y
A 5 0 0 0 A 0
A 4 8 × 1 0 0 1 A 1
A 3 Multiplier Y 0 1 0 A
A 2 0 1 1 A 2
A 1 1 0 0 A 3
A 4
0
1 0 1 A 5
1 1 0 A 6
1 1 1 A 7
S 2 S 1 S 0 Truth table of a 8 × 1 MUX
The logic circuit diagram of a 8 x 1 MUX is given below:
A 0
A 1
A 2
A 3
A
4
Y
A 5
A 6
A 7
S 2 S 1 S 0
Working Principle of 8 × 1 Multiplexer
The Boolean expression for output Y is:
Y = S '.S '.S '.A + S .S '.S '.A + S '.S .S '.A + S .S .S '.A + S '.S '.S A + S .S '.S A +S '.S .S .A + S .S .S .A 7
2
2
1
6
3
0
0
1
0
4
5
1
2
1
1
1
0
2
0
2
1
0
1
1
2
0
0
0
2
2
2
For example, say the selection switches are S = 0 S = 1 and S = 1 then other terms become 0 except 1.1.1. A and is
0
6
2
1
selected.
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Computer Hardware 81

