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29.  What is a half adder? Write the truth table and derive an SOP expression for sum and carry for a half adder.   [ISC 2019]
                Ans.  The half adder is a combinational circuit that is designed to perform the addition of two bits and produce the two binary outputs
                    as sum (S) and carry (C) bits. If A and B denote two inputs, then sum and carry are:
                                                      Input               Output
                                                   A         B        Sum       Carry
                                                   0         0         0         0
                                                   0         1         1         0
                                                   1         0         1         0
                                                   1         1         0         1
                 30.  Draw the logic diagram and truth table for a 2 input XNOR gate.                          [ISC 2017]
                Ans.      A          B          A⊙B            A
                          0          0           1                                  A⊙B
                          0          1           0             B
                          1          0           0
                          1          1           1          The Boolean expression of the two
                                                            variable XNOR gate is A'.B' + A.B.
                    Truth table of 2 variable XNOR gate
                     The logic circuit diagram of the two variables XNOR gate is as follows:

                     A              A.B
                     B
                                                   A'.B' + A.B

                    A'
                                   A'.B'
                    B'
                 31.  Draw the logic gate diagram for the reduced expression. Assume that the variables and their complements are available as
                    inputs.                                                                                    [ISC 2017]
                Ans.
                     A                A'
                                                   A'C
                                  C
                              A'                  A'B
                               B
                                                                       F
                                              B'
                                                       B'C
                                    C
                                            B'         AB'D'
                                 D
                     A                       D'
                 32.  Draw the logic gate diagram for the reduced expression. Assume that the variables and their complements are available as
                    inputs.                                                                                    [ISC 2017]
                Ans.  Logic gate diagram:
                     A
                                      A'+C'

                       C
                          A
                                      A'+D'              (A+C)(A+D)(B+D)

                          D
                       B
                                     B'+D'

                          D

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