Page 82 - Computer science 868 Class 12
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The block diagram and truth table of a 4 × 1 Multiplexer is given below:


                                                                                Inputs       Output
                                 A
                                  3
                                                                               S 1    S 0      Y
                                 A 2                  4 × 1                    0      0        A
                                                    Multiplier          Y      0      1        A 0
                                 A                                                              1
                                  1
                                                                               1      0        A 2
                                 A 0                                           1      1        A 3
                                                                            Truth table of 4 x 1 MUX




                                                      S 1  S 0

              To draw the logic circuit of a 4 × 1 Multiplexer we have to first draw the circuit of a 2 × 4 Decoder. Add four input lines
              with each of the AND gates. Now, pass the outputs of the four AND gates to a single OR gate. The circuit will be as
              follows:
                                               S 1       S 0








                                        A' 0



                                        A' 1



                                        A 2



                                        A 3





              Working Principle of 4 × 1 Multiplexer
              From the truth table, the Boolean expression for output Y can be written as:

              Y = S '.S '.A  +  S 'S .A  + S .S '.A  + S .S .A 3
                                       0
                                                0
                                             1
                                         2
                        0
                            1 0
                  1
                     0
                                 1
                                    1
              Say the state of selection switch S  = 1 and S  = 0 then output Y will be:
                                                      0
                                            1
              Y = 0.1.A  +  0.0.A  + 1.1.A  + 1.0.A 3
                                     2
                      0
                              1
              Or  Y = 0 + 0 + A  + 0
                            2
              From the high signal produced in the OR gate, it is evident that A  is selected in this example.
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